Difference between latch and flip-flop?

  • What is the difference between a latch and a flip-flop?

    What I am thinking is that a latch is equivalent to a flip-flop since it is used to store bits and is also equivalent to a register which is also used to store data. But after reading some articles on the internet I found differences between latches and flip-flops based on edge triggered and level sensitive functionality?

    What does that mean? Is a flip-flop the same as a latch or not?

  • The basic difference is a gating or clocking mechanism. For example, let us talk about SR latch and SR flip-flops.

    An SR Latch will look like this

    SR Latch using NAND gates

    In this circuit when you Set S as active the output Q would be high and Q' will be low. This is irrespective of anything else. (This is an active low circuit so active here means low, but for an active high circuit active would mean high)

    An SR Flip-Flop (also called gated or clocked SR latch) looks like this.

    enter image description here

    In this circuit the output is changed (i.e. the stored data is changed) only when you give a active clock signal. Otherwise, even if the S or R is active the data will not change. This mechanism is used to synchronize circuits and registers so that the data does not change unnecessarily.

    so can i conclude that latches are level triggered and flip flops are edge triggered?

    Latches are not triggered at all. As soon as I give input, I get the output in latches. Flipflops are triggered as in I have to give a clock trigger to convert my input into output.

    That is not a SR flip flop. That is a gated SR latch. The setup and hold times of this circuit will function just like any other latch with an "enable transparency" pin. A flip flop is a master-slave configuration. Just think about going from cycle to cycle with this latch. You cannot. You would need two latches with opposite phase clocks (hence a flip flop)

  • A flip flop is built from two back to back latches with opposite polarity clocks, which form a master slave topology.

    The type of latch is irrelevant (JK, SR, D, T) to this constraint, but it is important that the transparency is controlled by some pin (call it clock or enable or whatever you like).

    SR latches throw everyone for a loop because the most basic design is transparent all the time. So, once the clock enable is added people start calling it a flip flop. Well, it isn't; it is a gated latch. You can build a SR flip flop out of two gated SR latches however:

    true SR flip flop

    Or two JK latches:

    true jk ff

    Or two D latches: enter image description here

    Adding a clock pin to a latch (SR or JK) does not make it a flip flop -- it makes it a gated latch. Pulsing the clock to a gated latch does not make it a flip flop either; it makes it a pulse latch (pulse latch description).

    Flip flops are edge triggered and the setup and hold times are both relative to this active edge. A traditional flip flop will not allow any time borrowing through cycle borders, since the master-slave topology acts like a lock-and-dam system to create a hard edge at the active clock.

    Latches on the other hand setup to the transparency of the latch and hold until the latch closes. They also allow time borrowing through the entire transparency phase. This means that if one half cycle path is slow and the other half cycle path is fast; with a latch based design the slow path can borrow time into the fast paths cycle.

    A very common design trick when you need to squeeze every picosecond out of a path is to spread the flip flop apart (into two seperate latches) and do logic in between.

    Basically the setup and hold times are completely different between a latch and a flip flop; in terms of how the cycle boundaries are handled. The distinction is important if you do any latch based design. A lot of people (even on this site) will mix the two up. But once you start timing through them the difference becomes crystal clear.

    Also see:

    good text describing latches and flip flops

    What is a flip flop?


    Just showing a t-gate based D-flip flop (notice it is built from two back to back t-gate based D latches with opposite phase clocks).

    t-gate based d ff

    Hi jb going for the old revival badge? In my books a "latch" is an asynchronous memory register while a "flip flop" is a synchronous memory register , some with async features called Set/Reset. By de facto, all synchronous operations are edge sensitive.

    @TonyStewart.EEsince'75: Heh, Someone else answered right before me. Yes I am familiar with that definition but it is a bit handwavey. I think it is much clearer to realize that flip-flop is built from two latches with opposite phase clocks. This gives a very accurate picture of exactly what is happening inside and a greater understanding of the setup and hold times. It is an important distinction when characterizing standard cells or doing any custom data path design. It also leaves room for ambiguity:time borrowing flip flops,for example,have an asynchronous character around active clk edge.

    Replacing flops with pairs of latches that operate on different clock phases introduces the possibility of including dead time between those phases. If some chips activate their front-end latches only when their clock input is below (1/3)VDD, and the back-end latches only when the clock input is above (2/3)VDD, chips that share the same clock will be able to communicate reliably even if they don't see the clock switch at the exact same moment, provided that all chips have seen the clock rise above (1/3)VDD before any see it above (2/3)VDD. Such a design would seem to be...

    ...functionally better than a Schmidt trigger in just about every way; I wonder why it's more common for registers to use Schmidt triggers than split the front-end and back-end timing?

    @supercat: no one uses a schmidt trigger in CPU design, which is where most real speed path digital design is done. such a device is much larger, slower, and consumes more power. The regular latches and flip flops are easily characterized and margined. Maybe schmidt triggers are used on the matchline sense amplifiers or something but I don't work with that directly. But my answer was specifically for normal digital speedpaths which are multi-cycled

    FF's have TG's and Latches don't, but actually the synch fact makes all the difference. in any case it is a logic term not an an implementation term.. Logical names dont care how it is done.. e.g. SCR is a latch

    @jbord39: There are many scenarios where it's necessary to have a number of devices exchange data using clocks which are a lot slower than modern CPU clock speeds. If devices sample their inputs early on a clock edge, but don't switch their outputs until later on that clock edge, then in an application where two boards are communicating at 10Khz, one could use a slew rate as low as 0.1V/us without difficulty. On chips that use the same threshold for input sampling and output propagation, however, a slew rate that slow would likely cause unreliable behavior.

    @TonyStewart.EEsince'75: Actually both flip flops and latches can have t-gates. The distinction, again, is in the master-slave topology. I can confirm this as I have worked as a library designer for CPU standard cell libraries -- many latches have t-gates (most in fact). See the edit in my post for a standard schematic (t-gate based d-flip flop; again built from two back to back t-gate based d latches with opposite phase clocks).

    implementation arguments don't matter anyways, TTL and ECL are all different. the only significance is sync on edge

    @TonyStewart.EEsince'75: You made the t-gate argument, not me. You assume everyone works in the same design space as you. They don't. Some people actually design the CPU itself; and in this case the distinction between latch and flip flop becomes crucial (and neither ECL or TTL are used anymore ...). The proper definition is the master-slave topology. Otherwise how do you properly describe a time borrowing flip flop? It is edge triggered except for the transparency around the clock edge. Or how do you consider a pulse latch? It seems edge triggered ... yet still not a flip flop!!!

    yes but your answer , half of it is at least is 90%!physical ! implementation specific which is technically, irrelevant but interesting

    @TonyStewart.EEsince'75: Well, the verilog models obviously have to match the behavior of schematics. The fact that these are physical implementations doesn't change the real distinction -- the setup and hold time differences between latches and FF's (caused by master-slave topology). This occurs because the way FF's are made from two latches. Perhaps you can conceptualize a FF NOT made from latches -- but really it would act differently and no longer be a flip flop imo!

    if the context is an IC design environment, then the term imply physical attributes but the terms shud not deviate from their original meaning as I defined. one is asynchronous, the other sync

    > Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered). Although the term flip-flop has historically referred generically to both simple and clocked circuits, in modern usage it is common to reserve the term flip-flop exclusively for discussing clocked circuits; the simple ones are commonly called latches.< http://rfic.eecs.berkeley.edu/ee100/pdf/lect24.pdf

    @TonyStewart.EEsince'75: Frankly, most sources get this distinction wrong (they describe the edge vs. level triggered definition then go on to call a clocked latch a flip flop). In many cases the clear differentiation is not necessary. But once you start creating multicycle paths, it will become necessary to realize that a flip flop is two back to back latches. In fact the best static timing analysis or formal equivalence tools (both required for IC creation) treat the flip flops as two seperate latches. You simply cannot understand time borrowing without it.

    @TonyStewart.EEsince'75: This source describes the difference correctly. http://www.cs.ucr.edu/~ehwang/courses/cs120b/flipflops.pdf From an RTL standpoint you can get away being ignorant. At low MHz you can as well. But you cannot get away with it when you are actually designing the CPU multi-cycle circuits (10-11 stages of pipeline) which must all be synchronized with other less pipelined paths. If you take the time to read any source on time-borrowing you would quickly understand the difference.first google: http://www.vlsi-expert.com/2011/03/static-timing-analysis-sta-basic-part2.html

    agreed . cs.ucr.edu/~ehwang/courses/cs120b/flipflops.pdf repeats what I said

    +1. This is the best answer, IMO. The other ones, in a way or another, muddle the difference between edge-triggering (FF) and gating (gated latches). A bit heavy on the implementation side, especially for beginners. A nitpick: you seem to imply that the only technique for implementing edge triggering is coupling two latches in a master-slave configuration. I'm not an expert, but I think (IIRC) there are other tricks to implement edge-triggering.

    BTW, very good material that http://www.cs.ucr.edu/~ehwang/courses/cs120b/flipflops.pdf link. It would be nice if you could add a last paragraph in your answer with that link, just in case comments are deleted.

    @LorenzoDonati: Thanks. In regards to FF note: Not that I am aware of. You can pulse the clock signal to a latch and it resembles a flip flop (pulse latch), except you can run into some issues, for example the minimum pulse width never being less than the hold time of the latch under any circumstances, and a transparency window equal to the pulse width around the active clock (you just need to account for this). I added the link into my answer.

    Thanks for the feedback about FFs having always a master-slave internal structure. Now I need to update my "brain database" :-) (probably I still remembered those you call "pulsed latches", which I didn't know as a separate category, as being FFs).

    @jbord39 Your definition is not correct. A flip-flop is not always edge-triggered and does not always have a clock input, as you implied. You have other parts of your explanation incorrect as well.

    Here are definitions from "The Electronics Handbook" by Richard Dorf along with some additional commentary. A latch is "A memory element that does not have immunity to external feedback". To elaborate, a latch is a feedback circuit that has two stable states (aka bistable multivibrator) and can be used to store state information. A flip-flop is "A two-stage latch in a master-slave configuration." Both are, in nature, asynchronous sequential machines (i.e. state-machines). Either can be used asynchronously or synchronously. A latch that requires a clock is a "synchronous latch."

    "A standard DFF can either be used as an asynchronous SR latch, or can be used synchronously, with data and clock inputs." "It is often desirable to process information stored in memory elements and then restore the information in the memory element. If the memory element is a latch, the feedback would cause a problem. Signals can propagate around such a feedback loop an unknown number of times causing unknown results. A storage element that allows only one transit of the signal eliminates this indeterminacy. This can be provided by a two-stage configuration."

    @mrbean: i think you are quoting a singular source that you don't really understand. Most of what I said is in-line with this "electronics handbook", which I have never and will never read. I have worked for 3 years as a CPU library designer providing latches, flip flops, register files, and other memory elements and 2-3 years as a custom circuit designer using these memory elements. Everyone has a slightly different definition of what these things are. However, designing/tuning/characterizing them for setup/hold/delay will illuminate the differences.

  • A latch passes the input data thru directly in the open state, and freezes the output in the latched state. The latch responds to the level of the control signal.

    There are various types of flip-flops, but basically these change state on the edge of the control signal, and in some cases the data input(s). A classic D flip-flip is most like a latch, except it only looks at the input on a particular edge of the clock and freezes the output all the remaining time.

    so is there is any difference between latch and flip flop or not ?

    @ankur.trapasiya: Yes.

    hmmm... cleared somewhat..!! what i understood is flip flop needs a clock and a latch doesn't need it.

    @ankur.trapasiya: yes, latches don't have a clock input but they have a corresponding input: most of the time called ENABLE. The clock input of a D-Flip-Flop is edge sensitive, the enable input of a latch is level sensistive, i.e. the output changes when enable is active and the input changes.

    Latches having a clock input or enable is irrelevant. What you call the pin which means "enable transparency" does not correctly distinguish between the latch and flip flop. The correct distinction is that the flip flop crosses a cycle boundary while the latch crosses only a half cycle boundary (requiring two latches to create a flip flop).

    @Jbord: You are making this too complicated. Latches are level-gated, and flip-flops are edge-clocked. That's pretty much all that there is to it.

    @OlinLathrop: I would say that you are oversimplifying it by handwaving away the important distinctions. With this definition, how do you understand a time borrowing flip flop (flip flop with master latch clock delayed w.r.t to slave) which grants transparency around the triggering edge?

  • A latch is an example of a bistable multivibrator, that is, a device with exactly two stable states.
    These states are high-output and low-output.
    A latch has a feedback path, so information can be retained by the device.
    Therefore latches can be memory devices, and can store one bit of data for as long as the device is powered.
    As the name suggests, latches are used to "latch onto" information and hold in place.
    Latches are very similar to flip-flops, but are not synchronous devices, and do not operate on clock edges as flip-flops do.

    enter image description here

    A flip-flop is a device very like a latch in that it is a bistable mutivibrator, having two states and a feedback path that allows it to store a bit of information.
    The difference between a latch and a flip-flop is that a latch is asynchronous, and the outputs can change as soon as the inputs do (or at least after a small propagation delay).
    A flip-flop, on the other hand, is edge-triggered and only changes state when a control signal goes from high to low or low to high.
    This distinction is relatively recent and is not formal, with many authorities still referring to flip-flops as latches and vice versa, but it is a helpful distinction to make for the sake of clarity.

    enter image description here

    A latch is not a (bistable or any other) multivibrator.

  • The difference between latches and flip-flops is, their outputs are constantly affected by their inputs as long as the enable signal is present. When they are enabled, their content changes immediately when their inputs change. Flip-flops have their content change only either at the rising or trailing edge of the enable signal. This enable signal controls the clock signal. After the rising or trailing edge of the clock, the flip-flop content remains constant even if the input changes.

  • The difference is in the intended use, mostly. A flip-flop is a general idea and has variations - how it is triggered, JK inputs or D, and all that. Flips can be used for counters, shift registers and all the other uses found in texts and online articles about flip-flops.

    A latch is one particular use, where a set of flip flops (could be as few as one, I suppose) is given boolean levels, clocked, and thereafter hold those values constantly on their outputs. A snapshot, so to speak, of a binary value. No altering of the outputs values occur, except when new inputs are clocked in, or the latch is cleared which means setting all outputs to zero.

    D-type flip flops are the obvious choice, but exactly what you use or how it is triggered isn't vital to the idea of what a latch is, even if important in the particular circuit or chip you're designing or using.

  • A transparent latch is a device with a data input and a control input. The control input has two states which may be called "track" and "hold". Some devices will regard a "high" on the control input as "track" and a low input as "hold"; others do the opposite. Whenever the control input is in the "track" state, the state of the output will continuously attempt to follow the state of the data input (there will a short delay between the time the data input changes and the output reflects the change). If the control input goes from the "track" state to the "hold" state, provided that the last change to the data input has had a chance to reach the output, the output will hold its value until such time as the control input goes back to the "track" state.

    While transparent latches may be used in many ways, it's important to understand at least two usage scenarios. In one scenario, the latch is used to turn a signal that will sometimes hold valid data and sometimes hold invalid data, into a signal which will always hold valid data. This is done by keeping the latch in the "hold" state any time the data input might not match the desired output data. To change the latched data, one would put the desired data on the input, then set the latch briefly to "track" state and back to "hold" state, being careful that the data input does not change to an unwanted value while the "hold" signal is active. This arrangement could be used to e.g. control 64 outputs using eight control signals and eight data signals. Each control signal operates eight latches, one of which is wired to each of the eight data signals. One could use edge-triggered flip flops just as easily as latches, but the circuitry for a latch is somewhat simpler. Note that an edge-triggered flip flop in this scenario would ideally trigger on the transition from "hold" to "track".

    In the second usage scenario, the input may not be meaningful at the time the latch switches to "transparent", but will become meaningful prior to the latch switching to "hold". If the devices that use its output won't care about its state until some time after the latch has switched to "hold", then it will be the state of the data input at that time which will be fed to the output. One may be able to use an edge-triggered flip flop in this scenario, but it must trigger on the transition from "track" to "hold". Note that if the data input to the latch becomes valid a significant time before the transition from "hold" to "track", the output will do likewise. By contrast, the output of a flip flop would only become valid when the clock changed.

  • the main difference is latch is level triggered for which race around condition arises in JK-latch and T-latch where as there is no race around condition in JK-FF and T-FF..and flipflops are edge triggered so no race around condition in FF.

  • The main difference between latches and flip-flops is that for latches, their outputs are constantly affected by their inputs as long as the enable signal is asserted. In other words, when they are enabled, their content changes immediately when their inputs change. Flip-flops, on the other hand, have their content change only either at the rising or falling edge of the enable signal. This enable signal is usually the controlling clock signal. After the rising or falling edge of the clock, the flip-flop content remains constant even if the input changes

    This doesn't seem to add anything not already covered in Prasanth's answer that was posted over two years ago.

    @PeterJ: It does correct the grammar (original answer had an unresolved antecedent). Should have been an edit to the earlier answer, though.

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